PCI bus cartage consists of a alternation of PCI bus transactions. Each transaction consists of an abode appearance followed by one or added abstracts phases. The administration of the abstracts phases may be from architect to ambition (write transaction) or vice-versa (read transaction), but all of the abstracts phases accept to be in the aforementioned direction. Either affair may abeyance or arrest the abstracts phases at any point. (One accepted archetype is a low-performance PCI accessory that does not abutment admission transactions, and consistently halts a transaction afterwards the aboriginal abstracts phase.)
Any PCI accessory may admit a transaction. First, it accept to appeal permission from a PCI bus adjudicator on the motherboard. The adjudicator grants permission to one of the requesting devices. The architect begins the abode appearance by broadcasting a 32-bit abode additional a 4-bit command code, again waits for a ambition to respond. All added accessories appraise this abode and one of them responds a few cycles later.
64-bit acclamation is done application a two-stage abode phase. The architect broadcasts the low 32 abode bits, accompanied by a appropriate "dual abode cycle" command code. Accessories which do not abutment 64-bit acclamation can artlessly not accede to that command code. The next cycle, the architect transmits the top 32 abode bits, additional the absolute command code. The transaction operates analogously from that point on. To ensure affinity with 32-bit PCI devices, it is banned to use a bifold abode aeon if not necessary, i.e. if the high-order abode $.25 are all zero.
While the PCI bus transfers 32 $.25 per abstracts phase, the architect transmits a 4 byte accredit signals advertence which 8-bit bytes are to be advised significant. In particular, a abode accept to affect alone the enabled bytes in the ambition PCI device. They are of little accent for anamnesis reads, but I/O reads ability accept ancillary effects. The PCI accepted absolutely allows a abstracts appearance with no bytes enabled, which accept to behave as a no-op.
PCI abode spaces
PCI has three abode spaces: memory, I/O address, and configuration.
Memory addresses are 32 $.25 (optionally 64 bits) in size, abutment caching and can be admission transactions.
I/O addresses are for affinity with the Intel x86 architecture's I/O anchorage abode space. Although the PCI bus blueprint allows admission affairs in any abode space, a lot of accessories alone abutment it for anamnesis addresses and not I/O.
Finally, PCI agreement amplitude provides admission to 256 bytes of appropriate agreement registers per PCI device. Each PCI aperture gets its own agreement amplitude abode range. The registers are acclimated to configure accessories anamnesis and I/O abode ranges they should accede to from transaction initiators. When a computer is aboriginal angry on, all PCI accessories accede alone to their agreement amplitude accesses. The computers BIOS scans for accessories and assigns Anamnesis and I/O abode ranges to them.
If an abode is not claimed by any device, the transaction initiator's abode appearance will time out causing the architect to arrest the operation. In case of reads, it is accepted to accumulation all-ones for the apprehend abstracts bulk (0xFFFFFFFF) in this case. PCI accessories accordingly about attack to abstain application the all-ones bulk in important cachet registers, so that such an absurdity can be calmly detected by software.
PCI command codes
There are 16 accessible 4-bit command codes, and 12 of them are assigned. With the barring of the different bifold abode cycle, the atomic cogent bit of the command cipher indicates whether the afterward abstracts phases are a apprehend (data beatific from ambition to initiator) or a abode (data beatific from an architect to target). PCI targets accept to appraise the command cipher as able-bodied as the abode and not accede to abode phases which specify an bottomless command code.
The commands that accredit to accumulation curve depend on the PCI agreement amplitude accumulation band admeasurement annals getting set up properly; they may not be acclimated until that has been done.
0000
Arrest Acknowledge
This is a appropriate anatomy of apprehend aeon around addressed to the arrest controller, which allotment an arrest vector. The 32-bit abode acreage is ignored. One accessible accomplishing is to accomplish an arrest accede aeon on an ISA bus application a PCI/ISA bus bridge. This command is for IBM PC compatibility; if there is no Intel 8259 appearance arrest ambassador on the PCI bus, this aeon charge never be used.
0001
Appropriate Cycle
This aeon is a appropriate advertisement abode of arrangement contest that PCI agenda may be absorbed in. The abode acreage of a appropriate aeon is ignored, but it is followed by a abstracts appearance absolute a burden message. The currently authentic letters advertise that the processor is endlessly for some acumen (e.g. to save power). No accessory anytime responds to this cycle; it is consistently concluded with a adept arrest afterwards abrogation the abstracts on the bus for at atomic 4 cycles.
0010
I/O Read
This performs a apprehend from I/O space. All 32 $.25 of the apprehend abode are provided, so that a accessory can (for affinity reasons) apparatus beneath than 4 bytes account of I/O registers. If the byte enables appeal abstracts not aural the abode ambit accurate by the PCI accessory (e.g. a 4-byte apprehend from a accessory which alone supports 2 bytes of I/O abode space), it accept to be concluded with a ambition abort. Multiple abstracts cycles are permitted, application beeline (simple incrementing) admission ordering.
The PCI accepted is black the use of I/O amplitude in new devices, preferring that as abundant as accessible be done through capital anamnesis mapping.
0011
I/O Write
This performs a abode to I/O space.
010x
Reserved
A PCI accessory accept to not accede to an abode aeon with these command codes.
0110
Anamnesis Read
This performs a apprehend aeon from anamnesis space. Because the aboriginal anamnesis amplitude a PCI accessory is acceptable to apparatus is 16 bits, the two atomic cogent $.25 of the abode are not needed; agnate advice will admission in the anatomy of byte baddest signals. They instead specify the adjustment in which admission abstracts accept to be returned. If a accessory does not abutment the requested order, it accept to accommodate the aboriginal chat and again disconnect.
If a anamnesis amplitude is apparent as "prefetchable", again the ambition accessory accept to abstain the byte baddest signals on a anamnesis apprehend and consistently acknowledgment 32 accurate bits.
0111
Anamnesis Write
This operates analogously to a anamnesis read. The byte baddest signals are added important in a write, as unselected bytes accept to not be accounting to memory.
Generally, PCI writes are faster than PCI reads, because a accessory can absorber the admission abode abstracts and absolution the bus faster. For a read, it accept to adjournment the abstracts appearance until the abstracts has been fetched.
100x
Reserved
A PCI accessory accept to not accede to an abode aeon with these command codes.
1010
Agreement Read
This is agnate to an I/O read, but reads from PCI agreement space. A accessory accept to accede alone if the low 11 $.25 of the abode specify a action and annals that it implements, and if the appropriate IDSEL arresting is asserted. It accept to abstain the top 21 bits. Admission reads (using beeline incrementing) are acceptable in PCI agreement space.
Unlike I/O space, accepted PCI agreement registers are authentic so that reads never afflict the accompaniment of the device. It is accessible for a accessory to accept agreement amplitude registers above the accepted 64 bytes which accept apprehend ancillary effects, but this is rare.11
Agreement amplitude accesses generally accept a few cycles of adjournment in adjustment to acquiesce the IDSEL curve to stabilize, which makes them slower than added forms of access. Also, a agreement amplitude admission requires a multi-step operation rather than a individual apparatus instruction. Thus, it is best to abstain them during accepted operation of a PCI device.
1011
Agreement Write
This operates analogously to a agreement read.
1100
Anamnesis Apprehend Multiple
This command is identical to a all-encompassing anamnesis read, but includes the adumbration that a continued apprehend admission will abide above the end of the accepted accumulation line, and the ambition should internally prefetch a ample bulk of data. A ambition is consistently acceptable to accede this a analogue for a all-encompassing anamnesis read.
1101
Bifold Abode Cycle
When accessing a anamnesis abode that requires added than 32 $.25 to represent, the abode appearance begins with this command and the low 32 $.25 of the address, followed by a additional aeon with the absolute command and the top 32 $.25 of the address. PCI targets that do not abutment 64-bit acclamation can artlessly amusement this as addition aloof command cipher and not accede to it. This command cipher can alone be acclimated with a non-zero high-order abode word; it is banned to use this aeon if not necessary.
1110
Anamnesis Apprehend Line
This command is identical to a all-encompassing anamnesis read, but includes the adumbration that the apprehend will abide to the end of the accumulation line. A ambition is consistently acceptable to accede this a analogue for a all-encompassing anamnesis read.
1111
Anamnesis Abode and Invalidate
This command is identical to a all-encompassing anamnesis write, but comes with the agreement that one or added accomplished accumulation curve will be written, with all byte selects enabled. This is an enhancement for write-back caches concern the bus. Normally, a write-back accumulation captivation bedraggled abstracts accept to arrest the abode operation continued abundant abode its own bedraggled abstracts first. If the abode is performed application this command, the abstracts to be accounting aback is affirmed to be irrelevant, and can artlessly be invalidated in the write-back cache.
This enhancement alone affects the concern cache, and makes no aberration to the target, which may amusement this as a analogue for the anamnesis abode command.
Any PCI accessory may admit a transaction. First, it accept to appeal permission from a PCI bus adjudicator on the motherboard. The adjudicator grants permission to one of the requesting devices. The architect begins the abode appearance by broadcasting a 32-bit abode additional a 4-bit command code, again waits for a ambition to respond. All added accessories appraise this abode and one of them responds a few cycles later.
64-bit acclamation is done application a two-stage abode phase. The architect broadcasts the low 32 abode bits, accompanied by a appropriate "dual abode cycle" command code. Accessories which do not abutment 64-bit acclamation can artlessly not accede to that command code. The next cycle, the architect transmits the top 32 abode bits, additional the absolute command code. The transaction operates analogously from that point on. To ensure affinity with 32-bit PCI devices, it is banned to use a bifold abode aeon if not necessary, i.e. if the high-order abode $.25 are all zero.
While the PCI bus transfers 32 $.25 per abstracts phase, the architect transmits a 4 byte accredit signals advertence which 8-bit bytes are to be advised significant. In particular, a abode accept to affect alone the enabled bytes in the ambition PCI device. They are of little accent for anamnesis reads, but I/O reads ability accept ancillary effects. The PCI accepted absolutely allows a abstracts appearance with no bytes enabled, which accept to behave as a no-op.
PCI abode spaces
PCI has three abode spaces: memory, I/O address, and configuration.
Memory addresses are 32 $.25 (optionally 64 bits) in size, abutment caching and can be admission transactions.
I/O addresses are for affinity with the Intel x86 architecture's I/O anchorage abode space. Although the PCI bus blueprint allows admission affairs in any abode space, a lot of accessories alone abutment it for anamnesis addresses and not I/O.
Finally, PCI agreement amplitude provides admission to 256 bytes of appropriate agreement registers per PCI device. Each PCI aperture gets its own agreement amplitude abode range. The registers are acclimated to configure accessories anamnesis and I/O abode ranges they should accede to from transaction initiators. When a computer is aboriginal angry on, all PCI accessories accede alone to their agreement amplitude accesses. The computers BIOS scans for accessories and assigns Anamnesis and I/O abode ranges to them.
If an abode is not claimed by any device, the transaction initiator's abode appearance will time out causing the architect to arrest the operation. In case of reads, it is accepted to accumulation all-ones for the apprehend abstracts bulk (0xFFFFFFFF) in this case. PCI accessories accordingly about attack to abstain application the all-ones bulk in important cachet registers, so that such an absurdity can be calmly detected by software.
PCI command codes
There are 16 accessible 4-bit command codes, and 12 of them are assigned. With the barring of the different bifold abode cycle, the atomic cogent bit of the command cipher indicates whether the afterward abstracts phases are a apprehend (data beatific from ambition to initiator) or a abode (data beatific from an architect to target). PCI targets accept to appraise the command cipher as able-bodied as the abode and not accede to abode phases which specify an bottomless command code.
The commands that accredit to accumulation curve depend on the PCI agreement amplitude accumulation band admeasurement annals getting set up properly; they may not be acclimated until that has been done.
0000
Arrest Acknowledge
This is a appropriate anatomy of apprehend aeon around addressed to the arrest controller, which allotment an arrest vector. The 32-bit abode acreage is ignored. One accessible accomplishing is to accomplish an arrest accede aeon on an ISA bus application a PCI/ISA bus bridge. This command is for IBM PC compatibility; if there is no Intel 8259 appearance arrest ambassador on the PCI bus, this aeon charge never be used.
0001
Appropriate Cycle
This aeon is a appropriate advertisement abode of arrangement contest that PCI agenda may be absorbed in. The abode acreage of a appropriate aeon is ignored, but it is followed by a abstracts appearance absolute a burden message. The currently authentic letters advertise that the processor is endlessly for some acumen (e.g. to save power). No accessory anytime responds to this cycle; it is consistently concluded with a adept arrest afterwards abrogation the abstracts on the bus for at atomic 4 cycles.
0010
I/O Read
This performs a apprehend from I/O space. All 32 $.25 of the apprehend abode are provided, so that a accessory can (for affinity reasons) apparatus beneath than 4 bytes account of I/O registers. If the byte enables appeal abstracts not aural the abode ambit accurate by the PCI accessory (e.g. a 4-byte apprehend from a accessory which alone supports 2 bytes of I/O abode space), it accept to be concluded with a ambition abort. Multiple abstracts cycles are permitted, application beeline (simple incrementing) admission ordering.
The PCI accepted is black the use of I/O amplitude in new devices, preferring that as abundant as accessible be done through capital anamnesis mapping.
0011
I/O Write
This performs a abode to I/O space.
010x
Reserved
A PCI accessory accept to not accede to an abode aeon with these command codes.
0110
Anamnesis Read
This performs a apprehend aeon from anamnesis space. Because the aboriginal anamnesis amplitude a PCI accessory is acceptable to apparatus is 16 bits, the two atomic cogent $.25 of the abode are not needed; agnate advice will admission in the anatomy of byte baddest signals. They instead specify the adjustment in which admission abstracts accept to be returned. If a accessory does not abutment the requested order, it accept to accommodate the aboriginal chat and again disconnect.
If a anamnesis amplitude is apparent as "prefetchable", again the ambition accessory accept to abstain the byte baddest signals on a anamnesis apprehend and consistently acknowledgment 32 accurate bits.
0111
Anamnesis Write
This operates analogously to a anamnesis read. The byte baddest signals are added important in a write, as unselected bytes accept to not be accounting to memory.
Generally, PCI writes are faster than PCI reads, because a accessory can absorber the admission abode abstracts and absolution the bus faster. For a read, it accept to adjournment the abstracts appearance until the abstracts has been fetched.
100x
Reserved
A PCI accessory accept to not accede to an abode aeon with these command codes.
1010
Agreement Read
This is agnate to an I/O read, but reads from PCI agreement space. A accessory accept to accede alone if the low 11 $.25 of the abode specify a action and annals that it implements, and if the appropriate IDSEL arresting is asserted. It accept to abstain the top 21 bits. Admission reads (using beeline incrementing) are acceptable in PCI agreement space.
Unlike I/O space, accepted PCI agreement registers are authentic so that reads never afflict the accompaniment of the device. It is accessible for a accessory to accept agreement amplitude registers above the accepted 64 bytes which accept apprehend ancillary effects, but this is rare.11
Agreement amplitude accesses generally accept a few cycles of adjournment in adjustment to acquiesce the IDSEL curve to stabilize, which makes them slower than added forms of access. Also, a agreement amplitude admission requires a multi-step operation rather than a individual apparatus instruction. Thus, it is best to abstain them during accepted operation of a PCI device.
1011
Agreement Write
This operates analogously to a agreement read.
1100
Anamnesis Apprehend Multiple
This command is identical to a all-encompassing anamnesis read, but includes the adumbration that a continued apprehend admission will abide above the end of the accepted accumulation line, and the ambition should internally prefetch a ample bulk of data. A ambition is consistently acceptable to accede this a analogue for a all-encompassing anamnesis read.
1101
Bifold Abode Cycle
When accessing a anamnesis abode that requires added than 32 $.25 to represent, the abode appearance begins with this command and the low 32 $.25 of the address, followed by a additional aeon with the absolute command and the top 32 $.25 of the address. PCI targets that do not abutment 64-bit acclamation can artlessly amusement this as addition aloof command cipher and not accede to it. This command cipher can alone be acclimated with a non-zero high-order abode word; it is banned to use this aeon if not necessary.
1110
Anamnesis Apprehend Line
This command is identical to a all-encompassing anamnesis read, but includes the adumbration that the apprehend will abide to the end of the accumulation line. A ambition is consistently acceptable to accede this a analogue for a all-encompassing anamnesis read.
1111
Anamnesis Abode and Invalidate
This command is identical to a all-encompassing anamnesis write, but comes with the agreement that one or added accomplished accumulation curve will be written, with all byte selects enabled. This is an enhancement for write-back caches concern the bus. Normally, a write-back accumulation captivation bedraggled abstracts accept to arrest the abode operation continued abundant abode its own bedraggled abstracts first. If the abode is performed application this command, the abstracts to be accounting aback is affirmed to be irrelevant, and can artlessly be invalidated in the write-back cache.
This enhancement alone affects the concern cache, and makes no aberration to the target, which may amusement this as a analogue for the anamnesis abode command.
No comments:
Post a Comment