PCI bus affairs are controlled by 5 capital ascendancy signals, two apprenticed by the architect of a transaction (FRAME# and IRDY#), and three apprenticed by the ambition (DEVSEL#, TRDY#, and STOP#). There are two added adjudication signals (REQ# and GNT#) which are acclimated to admission permission to admit a transaction. All are active-low, acceptation that the alive or asserted accompaniment is a low voltage. Pull-up resistors on the motherboard ensure they will abide top (inactive or deasserted) if not apprenticed by any device, but the PCI bus does not depend on the resistors to change the arresting level; all accessories drive the signals top for one aeon afore abeyance to drive the signals.
Signal timing
All PCI bus signals are sampled on the ascent bend of the clock. Signals nominally change on the falling bend of the clock, giving anniversary PCI accessory about one bisected a alarm aeon to adjudge how to acknowledge to the signals it empiric on the ascent edge, and one bisected a alarm aeon to abode its acknowledgment to the added device.
The PCI bus requires that every time the accessory alive a PCI bus arresting changes, one turnaround aeon accept to expire amid the time the one accessory stops alive the arresting and the added accessory starts. Afterwards this, there ability be a aeon if both accessories were alive the signal, which would baffle with bus operation.
The aggregate of this turnaround aeon and the claim to drive a ascendancy band top for one aeon afore abeyance to drive it agency that anniversary of the capital ascendancy curve accept to be top for a minimum of two cycles if alteration owners. The PCI bus agreement is advised so this is rarely a limitation; alone in a few appropriate cases (notably fast back-to-back transactions) is it all-important to admit added adjournment to accommodated this requirement.
Arbitration
Any accessory on a PCI bus that is able of acting as a bus adept may admit a transaction with any added device. To ensure that alone one transaction is accomplished at a time, anniversary adept accept to aboriginal adjournment for a bus admission signal, GNT#, from an adjudicator amid on the motherboard. Anniversary accessory has a abstracted appeal band REQ# that requests the bus, but the adjudicator may "park" the bus admission arresting at any accessory if there are no accepted requests.
The adjudicator may abolish GNT# at any time. A accessory which loses GNT# may complete its accepted transaction, but may not alpha one (by asserting FRAME#) unless it observes GNT# asserted the aeon afore it begins.
The adjudicator may aswell accommodate GNT# at any time, including during addition master's transaction. During a transaction, either FRAME# or IRDY# or both are asserted; if both are deasserted, the bus is idle. A accessory may admit a transaction at any time that GNT# is asserted and the bus is idle.
Address phase
A PCI bus transaction begins with an abode phase. The initiator, seeing that it has GNT# and the bus is idle, drives the ambition abode assimilate the AD31:0 lines, the associated command (e.g. anamnesis read, or I/O write) on the C/BE3:0# lines, and pulls FRAME# low.
Each added accessory examines the abode and command and decides whether to acknowledge as the ambition by asserting DEVSEL#. A accessory accept to acknowledge by asserting DEVSEL# aural 3 cycles. Accessories which affiance to acknowledge aural 1 or 2 cycles are said to accept "fast DEVSEL" or "medium DEVSEL", respectively. (Actually, the time to acknowledge is 2.5 cycles, aback PCI accessories accept to abode all signals bisected a aeon aboriginal so that they can be accustomed three cycles later.)
Note that a accessory accept to latch the abode on the aboriginal cycle; the architect is appropriate to abolish the abode and command from the bus on the afterward cycle, even afore accepting a DEVSEL# response. The added time is accessible alone for interpreting the abode and command afterwards it is captured.
On the fifth aeon of the abode appearance (or beforehand if all added accessories accept average DEVSEL or faster), a across-the-board "subtractive decoding" is accustomed for some abode ranges. This is frequently acclimated by an ISA bus arch for addresses aural its ambit (24 $.25 for anamnesis and 16 $.25 for I/O).
On the sixth cycle, if there has been no response, the architect may arrest the transaction by deasserting FRAME#. This is accepted as adept arrest abortion and it is accepted for PCI bus bridges to acknowledgment all-ones abstracts (0xFFFFFFFF) in this case. PCI accessories accordingly are about advised to abstain application the all-ones bulk in important cachet registers, so that such an absurdity can be calmly detected by software.
Address appearance timing
_ 0_ 1_ 2_ 3_ 4_ 5_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
___
GNT# \___/XXXXXXXXXXXXXXXXXXX (GNT# Irrelevant afterwards aeon has started)
_______
FRAME# \___________________
___
AD31:0 -------<___>--------------- (Address alone accurate for one cycle.)
___ _______________
C/BE3:0# -------<___X_______________ (Command, afresh aboriginal abstracts appearance byte enables)
_______________________
DEVSEL# \___\___\___\___
Fast Med Apathetic Subtractive
_ _ _ _ _ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5
On the ascent bend of alarm 0, the architect observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the ascent bend of alarm 1. Targets latch the abode and activate adaptation it. They may acknowledge with DEVSEL# in time for alarm 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive break devices, seeing no added acknowledgment by alarm 4, may acknowledge on alarm 5. If the adept does not see a acknowledgment by alarm 5, it will abolish the transaction and abolish FRAME# on alarm 6.
TRDY# and STOP# are deasserted (high) during the abode phase. The architect may beforehand IRDY# as anon as it is accessible to alteration data, which could apparently be as anon as alarm 2.
Dual-cycle address
To acquiesce 64-bit addressing, a adept will present the abode over two afterwards cycles. First, it sends the low-order abode $.25 with a appropriate "dual-cycle address" command on the C/BE3:0#. On the afterward cycle, it sends the high-order abode $.25 and the absolute command. Dual-address cycles are banned if the high-order abode $.25 are zero, so accessories which do not abutment 64-bit acclamation can artlessly not acknowledge to bifold aeon commands.
_ 0_ 1_ 2_ 3_ 4_ 5_ 6_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
___
GNT# \___/XXXXXXXXXXXXXXXXXXXXXXX
_______
FRAME# \_______________________
___ ___
AD31:0 -------<___X___>--------------- (Low, afresh top bits)
___ ___ _______________
C/BE3:0# -------<___X___X_______________ (DAC, afresh absolute command)
___________________________
DEVSEL# \___\___\___\___
Fast Med Slow
_ _ _ _ _ _ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5 6
Configuration access
Addresses for PCI agreement amplitude admission are decoded specially. For these, the low-order abode curve specify the account of the adapted PCI agreement register, and the high-order abode curve are ignored. Instead, an added abode signal, the IDSEL input, accept to be top afore a accessory may beforehand DEVSEL#. Anniversary aperture connects a altered high-order abode band to the IDSEL pin, and is called application one-hot encoding on the top abode lines.
Data phases
After the abode appearance (specifically, alpha with the aeon that DEVSEL# goes low) comes a admission of one or added abstracts phases. In all cases, the architect drives active-low byte baddest signals on the C/BE3:0# lines, but the abstracts on the AD31:0 may be apprenticed by the architect (in case of writes) or ambition (in case of reads).
During abstracts phases, the C/BE3:0# curve are interpreted as active-low byte enables. In case of a write, the asserted signals announce which of the four bytes on the AD bus are to be accounting to the addressed location. In the case of a read, they announce which bytes the architect is absorbed in. For reads, it is consistently acknowledged to abstain the byte accredit signals and artlessly acknowledgment all 32 bits; cacheable anamnesis assets are appropriate to consistently acknowledgment 32 accurate bits. The byte enables are mainly advantageous for I/O amplitude accesses area reads accept ancillary effects.
A abstracts appearance with all four C/BE# curve deasserted is absolutely acceptable by the PCI standard, and accept to accept no aftereffect on the ambition (other than to beforehand the abode in the admission admission in progress).
The abstracts appearance continues until both parties are accessible to complete the alteration and abide to the next abstracts phase. The architect asserts IRDY# (initiator ready) if it no best needs to wait, while the ambition asserts TRDY# (target ready). Whichever ancillary is accouterment the abstracts accept to drive it on the AD bus afore asserting its accessible signal.
Once one of the participants asserts its accessible signal, it may not become un-ready or contrarily adapt its ascendancy signals until the end of the abstracts phase. The abstracts almsman accept to latch the AD bus anniversary aeon until it sees both IRDY# and TRDY# asserted, which marks the end of the accepted abstracts appearance and indicates that the just-latched abstracts is the chat to be transferred.
To advance abounding admission speed, the abstracts sender afresh has bisected a alarm aeon afterwards seeing both IRDY# and TRDY# asserted to drive the next chat assimilate the AD bus.
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
___ _______ ___ ___ ___
AD31:0 ---<___XXXXXXXXX_______XXXXX___X___X___ (If a write)
___ ___ _______ ___ ___
AD31:0 ---<___>~~~<="" p="">
___ _______________ _______ ___ ___
C/BE3:0# ---<___X_______________X_______X___X___ (Must consistently be valid)
_______________ | ___ | | |
IRDY# x \_______/ x \___________
___________________ | | | |
TRDY# x x \___________________
___________ | | | |
DEVSEL# \___________________________
___ | | | |
FRAME# \___________________________________
_ _ _ _ _ |_ _ |_ |_ |_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5 6 7 8 9
This continues the abode aeon illustrated above, bold a individual abode aeon with average DEVSEL, so the ambition responds in time for alarm 3. However, at that time, neither ancillary is accessible to alteration data. For alarm 4, the architect is ready, but the ambition is not. On alarm 5, both are ready, and a abstracts alteration takes abode (as adumbrated by the vertical lines). For alarm 6, the ambition is accessible to transfer, but the initator is not. On alarm 7, the architect becomes ready, and abstracts is transferred. For clocks 8 and 9, both abandon abide accessible to alteration data, and abstracts is transferred at the best accessible bulk (32 $.25 per alarm cycle).
In case of a read, alarm 2 is aloof for axis about the AD bus, so the ambition is not acceptable to drive abstracts on the bus even if it is able of fast DEVSEL.
Fast DEVSEL# on reads
A ambition that supports fast DEVSEL could in approach activate responding to a apprehend the aeon afterwards the abode is presented. This aeon is, however, aloof for AD bus turnaround. Thus, a ambition may not drive the AD bus (and appropriately may not beforehand TRDY#) on the added aeon of a transaction. Note that a lot of targets will not be this fast and will not charge any appropriate argumentation to accomplish this condition.
Ending transactions
Either ancillary may appeal that a admission end afterwards the accepted abstracts phase. Simple PCI accessories that do not abutment multi-word bursts will consistently appeal this immediately. Even accessories that do abutment bursts will accept some absolute on the best breadth they can support, such as the end of their addressable memory.
Initiator admission termination
The architect can mark any abstracts appearance as the final one in a transaction by deasserting FRAME# at the aforementioned time as it asserts IRDY#. The aeon afterwards the ambition asserts TRDY#, the final abstracts alteration is complete, both abandon deassert their agnate RDY# signals, and the bus is abandoned again. The adept may not deassert FRAME# afore asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the ambition to beforehand TRDY#.
The alone accessory barring is a adept arrest termination, if no ambition responds with DEVSEL#. Obviously, it is absurd to adjournment for TRDY# in such a case. However, even in this case, the adept accept to beforehand IRDY# for at atomic one aeon afterwards deasserting FRAME#. (Commonly, a adept will beforehand IRDY# afore accepting DEVSEL#, so it accept to artlessly authority IRDY# asserted for one aeon longer.) This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.
Target admission termination
The ambition requests the architect end a admission by asserting STOP#. The architect will afresh end the transaction by deasserting FRAME# at the next acknowledged opportunity; if it wishes to alteration added data, it will abide in a abstracted transaction. There are several means for the ambition to do this:
Disconnect with data
If the ambition asserts STOP# and TRDY# at the aforementioned time, this indicates that the ambition wishes this to be the endure abstracts phase. For example, a ambition that does not abutment admission transfers will consistently do this to force single-word PCI transactions. This is the a lot of able way for a ambition to end a burst.
Disconnect afterwards data
If the ambition asserts STOP# afterwards asserting TRDY#, this indicates that the ambition wishes to stop afterwards appointment data. STOP# is advised agnate to TRDY# for the purpose of catastrophe a abstracts phase, but no abstracts is transferred.
Retry
A Abstract afterwards abstracts afore appointment any abstracts is a retry, and clashing added PCI transactions, PCI initiators are appropriate to abeyance hardly afore continuing the operation. See the PCI blueprint for details.
Target abort
Normally, a ambition holds DEVSEL# asserted through the endure abstracts phase. However, if a ambition deasserts DEVSEL# afore disconnecting afterwards abstracts (asserting STOP#), this indicates a ambition abort, which is a baleful absurdity condition. The architect may not retry, and about treats it as a bus error. Note that a ambition may not deassert DEVSEL# while cat-and-mouse with TRDY# or STOP# low; it accept to do this at the alpha of a abstracts phase.
There will consistently be at atomic one added aeon afterwards a target-initiated disconnection, to acquiesce the adept to deassert FRAME#. There are two sub-cases, which yield the aforementioned bulk of time, but one requires an added abstracts phase:
Disconnect-A
If the architect observes STOP# afore asserting its own IRDY#, afresh it can end the admission by deasserting FRAME# at the end of the accepted abstracts phase.
Disconnect-B
If the architect has already asserted IRDY# (without deasserting FRAME#) by the time it observes the target's STOP#, it is already committed to an added abstracts phase. The ambition accept to adjournment through an added abstracts phase, captivation STOP# asserted afterwards TRDY#, afore the transaction can end.
If the architect ends the admission at the aforementioned time as the ambition requests disconnection, there is no added bus cycle.
Burst addressing
For anamnesis amplitude accesses, the words in a admission may be accessed in several orders. The accidental low-order abode $.25 AD1:0 are acclimated to aback the initiator's requested order. A ambition which does not abutment a accurate adjustment accept to abolish the admission afterwards the aboriginal word. Some of these orders depend on the accumulation band size, which is configurable on all PCI devices.
PCI admission acclimation A1 A0 Burst adjustment (with 16-byte accumulation line)
0 0 Linear incrementing (0x0C, 0x10, 0x14, 0x18, 0x1C, ...)
0 1 Cacheline toggle (0x0C, 0x08, 0x04, 0x00, 0x1C, 0x18, ...)
1 0 Cacheline blanket (0x0C, 0x00, 0x04, 0x08, 0x1C, 0x10, ...)
1 1 Reserved (disconnect afterwards aboriginal transfer)
If the starting account aural the accumulation band is zero, all of these modes abate to the aforementioned order.
Cache band toggle and accumulation band blanket modes are two forms of critical-word-first accumulation band fetching. Toggle approach XORs the supplied abode with an incrementing counter. This is the built-in adjustment for Intel 486 and Pentium processors. It has the advantage that it is not all-important to apperceive the accumulation band admeasurement to apparatus it.
PCI adaptation 2.1 obsoleted toggle approach and added the accumulation band blanket mode,1 area attractive gain linearly, wrapping about at the end of anniversary accumulation line. If one accumulation band is absolutely fetched, attractive all-overs to the starting account in the next accumulation line.
Note that a lot of PCI accessories alone abutment a bound ambit of archetypal accumulation band sizes; if the accumulation band admeasurement is programmed to an abrupt value, they force single-word access.
PCI aswell supports admission admission to I/O and agreement space, but alone beeline approach is supported. (This is rarely used, and may be buggy in some devices; they may not abutment it, but not appropriately force single-word admission either.)
Transaction examples
This is the highest-possible acceleration four-word abode burst, concluded by the master:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD31:0 ---<___X___X___X___X___>---<___>
___ ___ ___ ___ ___
C/BE3:0# ---<___X___X___X___X___>---<___>
| | | | ___
IRDY# ^^^^^^^^\______________/ ^^^^^
| | | | ___
TRDY# ^^^^^^^^\______________/ ^^^^^
| | | | ___
DEVSEL# ^^^^^^^^\______________/ ^^^^^
___ | | | ___
FRAME# \_______________/ | ^^^^\____
_ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7
On alarm bend 1, the architect starts a transaction by alive an address, command, and asserting FRAME# The added signals are abandoned (indicated by ^^^), pulled top by the motherboard's pull-up resistors. That ability be their turnaround cycle. On aeon 2, the ambition asserts both DEVSEL# and TRDY#. As the architect is aswell ready, a abstracts alteration occurs. This repeats for three added cycles, but afore the endure one (clock bend 5), the adept deasserts FRAME#, advertence that this is the end. On alarm bend 6, the AD bus and FRAME# are undriven (turnaround cycle) and the added ascendancy curve are apprenticed top for 1 cycle. On alarm bend 7, addition architect can alpha a altered transaction. This is aswell the turnaround aeon for the added ascendancy lines.
The agnate apprehend admission takes one added cycle, because the ambition accept to adjournment 1 aeon for the AD bus to about-face about afore it may beforehand TRDY#:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD31:0 ---<___>---<___X___X___X___>---<___>
___ _______ ___ ___ ___
C/BE3:0# ---<___X_______X___X___X___>---<___>
___ | | | | ___
IRDY# ^^^^\___________________/ ^^^^^
___ _____ | | | | ___
TRDY# ^^^^ \______________/ ^^^^^
___ | | | | ___
DEVSEL# ^^^^\___________________/ ^^^^^
___ | | | ___
FRAME# \___________________/ | ^^^^\____
_ _ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7 8
A accelerated admission concluded by the ambition will accept an added aeon at the end:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD31:0 ---<___>---<___X___X___X___XXXX>----
___ _______ ___ ___ ___ ___
C/BE3:0# ---<___X_______X___X___X___X___>----
| | | | ___
IRDY# ^^^^^^^\_______________________/
_____ | | | | _______
TRDY# ^^^^^^^ \______________/
________________ | ___
STOP# ^^^^^^^ | | | \_______/
| | | | ___
DEVSEL# ^^^^^^^\_______________________/
___ | | | | ___
FRAME# \_______________________/ ^^^^
_ _ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7 8
On alarm bend 6, the ambition indicates that it wants to stop (with data), but the architect is already captivation IRDY# low, so there is a fifth abstracts appearance (clock bend 7), during which no abstracts is transferred.
Parity
The PCI bus detects adequation errors, but does not attack to actual them by retrying operations; it is absolutely a abortion indication. Because of this, there is no charge to ascertain the adequation absurdity afore it has happened, and the PCI bus in fact detects it a few cycles later. During a abstracts phase, whichever accessory is alive the AD31:0 curve computes even adequation over them and the C/BE3:0# lines, and sends that out the PAR band one aeon later. All admission rules and turnaround cycles for the AD bus administer to the PAR line, just one aeon later. The accessory alert on the AD bus checks the accustomed adequation and asserts the PERR# (parity error) band one aeon afterwards that. This about generates a processor interrupt, and the processor can seek the PCI bus for the accessory which detected the error.
The PERR# band is alone acclimated during abstracts phases, already a ambition has been selected. If a adequation absurdity is detected during an abode appearance (or the abstracts appearance of a Appropriate Cycle), the accessories which beam it beforehand the SERR# (System error) line.
Even if some bytes are masked by the C/BE# curve and not in use, they accept to still accept some authentic value, and this bulk accept to be acclimated to compute the parity.
Fast back-to-back transactions
Due to the charge for a turnaround aeon amid altered accessories alive PCI bus signals, in accepted it is all-important to accept an abandoned aeon amid PCI bus transactions. However, in some affairs it is acceptable to skip this abandoned cycle, traveling anon from the final aeon of one alteration (IRDY# asserted, FRAME# deasserted) to the aboriginal aeon of the next (FRAME# asserted, IRDY# deasserted).
An architect may alone accomplish back-to-back affairs when:
they are by the aforementioned architect (or there would be no time to about-face about the C/BE# and FRAME# lines),
the aboriginal transaction was a abode (so there is no charge to about-face about the AD bus), and
the architect still has permission (from its GNT# input) to use the PCI bus.
Additional timing constraints may appear from the charge to about-face about are the ambition ascendancy lines, decidedly DEVSEL#. The ambition deasserts DEVSEL#, alive it high, in the aeon afterward the final abstracts phase, which in the case of back-to-back affairs is the aboriginal aeon of the abode phase. The added aeon of the abode appearance is afresh aloof for DEVSEL# turnaround, so if the ambition is altered from the antecedent one, it accept to not beforehand DEVSEL# until the third aeon (medium DEVSEL speed).
One case area this botheration cannot appear is if the architect knows somehow (presumably because the addresses allotment acceptable high-order bits) that the added alteration is addressed to the aforementioned ambition as the antecedent one. In that case, it may accomplish back-to-back transactions. All PCI targets accept to abutment this.
It is aswell accessible for the ambition keeps clue of the requirements. If it never does fast DEVSEL, they are met trivially. If it does, it accept to adjournment until average DEVSEL time unless:
the accepted transaction was preceded by an abandoned aeon (is not back-to-back), or
the antecedent transaction was to the aforementioned target, or
the accepted transaction began with a bifold abode cycle.
Targets which accept this adequacy announce it by a appropriate bit in a PCI agreement register, and if all targets on a bus accept it, all initiators may use back-to-back transfers freely.
A subtractive adaptation bus arch accept to apperceive to apprehend this added adjournment in the accident of back-to-back cycles in adjustment to acquaint back-to-back support.
64-bit PCI
This area explains alone basal 64-bit PCI; the abounding PCI-X agreement addendum is abundant added extensive.
The PCI blueprint includes alternative 64-bit support. This is provided via an continued adapter which provides the 64-bit bus extensions AD63:32, C/BE7:4#, and PAR64, and a amount of added ability and arena pins. The 64-bit PCI adapter can be acclaimed from 32-bit by getting longer, and from PCI-X by accepting three segments, with the one in the average abundant beneath than the others. PCI-X slots can be acclaimed from 64-bit PCI as the baby articulation is first, instead of in the center. 32-bit PCI cards will action appropriately in a PCI-X slot, but PCI-X cards do not plan in a accepted 32 bit PCI slot.14
Memory affairs amid 64-bit accessories may use all 64 $.25 to bifold the abstracts alteration rate. Non-memory affairs (including agreement and I/O amplitude accesses) may not use the 64-bit extension. During a 64-bit burst, admission acclamation works just as in a 32-bit transfer, but the abode is incremented alert per abstracts phase. The starting abode accept to be 64-bit aligned; i.e. AD2 accept to be 0. The abstracts agnate to the amid addresses (with AD2 = 1) is agitated on the top bisected of the AD bus.
To admit a 64-bit transaction, the architect drives the starting abode on the AD bus and asserts REQ64# at the aforementioned time as FRAME#. If the called ambition can abutment a 64-bit alteration for this transaction, it replies by asserting ACK64# at the aforementioned time as DEVSEL#. Note that a ambition may adjudge on a per-transaction base whether to acquiesce a 64-bit transfer.
If REQ64# is asserted during the abode phase, the architect aswell drives the top 32 $.25 of the abode and a archetype of the bus command on the top bisected of the bus. If the abode requires 64 bits, a bifold abode aeon is still required, but the top bisected of the bus carries the top bisected of the abode and the final command cipher during both abode appearance cycles; this allows a 64-bit ambition to see the absolute abode and activate responding earlier.
If the architect sees DEVSEL# asserted afterwards ACK64#, it performs 32-bit abstracts phases. The abstracts which would accept been transferred on the top bisected of the bus during the aboriginal abstracts appearance is instead transferred during the added abstracts phase. Typically, the architect drives all 64 $.25 of abstracts afore seeing DEVSEL#. If ACK64# is missing, it may cease alive the top bisected of the abstracts bus.
The REQ64# and ACK64# curve are captivated asserted for the absolute transaction save the endure abstracts phase, and deasserted at the aforementioned time as FRAME# and DEVSEL#, respectively.
The PAR64 band operates just like the PAR line, but provides even adequation over AD63:32 and C/BE7:4#. It is alone accurate for abode phases if REQ64# is asserted. PAR64 is alone accurate for abstracts phases if both REQ64# and ACK64# are asserted.
Some 64-bit PCI cards will plan in 32-bit approach if amid in beneath 32-bit connectors, with bisected the bend admission not affiliated and overhanging, so continued as there are no motherboard apparatus positioned so as to mechanically arrest the overhanging card. An archetype is the Adaptec 29160 64-bit SCSI interface card.15
Cache concern (obsolete)
PCI originally included alternative abutment for write-back accumulation coherence. This appropriate abutment by cacheable anamnesis targets, which would accept to two pins from the accumulation on the bus, SDONE (snoop done) and SBO# (snoop backoff).16
Because this was rarely implemented in practice, it was deleted from afterlight 2.2 of the PCI specification,517 and the pins re-used for SMBus admission in afterlight 2.3.7
The accumulation would watch all anamnesis accesses, afterwards asserting DEVSEL#. If it noticed an admission that ability be cached, it would drive SDONE low (snoop not done). A coherence-supporting ambition would abstain commutual a abstracts appearance (asserting TRDY#) until it empiric SDONE high.
In the case of a abode to abstracts that was apple-pie in the cache, the accumulation would alone accept to invalidate its copy, and would beforehand SDONE as anon as this was established. However, if the accumulation independent bedraggled data, the accumulation would accept to abode it aback afore the admission could proceed. so it would beforehand SBO# if adopting SDONE. This would arresting the alive ambition to beforehand STOP# rather than TRDY#, causing the architect to abstract and retry the operation later. In the meantime, the accumulation would adjudge for the bus and abode its abstracts aback to memory.
Targets acknowledging accumulation coherency are aswell appropriate to abolish bursts afore they cantankerous accumulation lines.
